Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model
نویسندگان
چکیده
In recent years, dynamic reconfigurable processor which can achieve reconfiguration with a few cycles is proposed. The fast reconfiguration makes run-time reconfiguration possible, and the run-time reconfiguration gives a new possibility to the dynamic reconfigurable processor, i.e. the dynamic reconfigurable processor can also execute partitioned independent subtasks with repeated reconfigurations and executions. However, to achieve an execution with the run-time reconfiguration, performance should be evaluated with various overheads: reconfiguration, memory accesses, etc. The overheads depend on reconfigurable architectures, and it is generally difficult to evaluate the overhead. As the overhead may critically affect the performance, designers should carefully explore design space for suitable architectures. In this paper, we propose a dynamic reconfigurable architecture exploration method based on Parameterized Reconfigurable Processor model (PRP-model) and task partitioning optimization algorithm for architecture exploration corresponding to proposed PRP-model. Experimental results showed that the proposed PRP-model and the task partitioning algorithm for PRP-model can fast evaluate various reconfigurable architectures, and designers can easily find suitable reconfigurable architectures by changing the PRPmodel parameters.
منابع مشابه
Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework Methodology for Rapid Accelerator Development Applied to Financial Applications A Reconfigurable Application Specific Instruction Set Processor. Adaptive processor architecture invited paperMichael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Cross-architectura...
متن کاملA Modeling method for Reconfigurable Processor Performance Analysis
Coarse grained reconfigurable architecture (CGRA) has become an important solution for high performance computing because of its high speed up ratio for computation intensive applications, fast configuration, good adaptability and low power consumption. However, the traditional performance analysis method of register transfer level modeling is simulating, which is still widely used. To overcome...
متن کاملOptimized Reconfigurable MAC Processor Architecture
Inefficient resources utilization is met in various embedded communication devices, which are based on standard processor cores and custom hardware modules. This paper addresses the inefficient resources utilization problem in MAC processor designs and presents a solution that is based on reconfigurable processor architecture and on dynamic-static instruction partitioning, depending on medium a...
متن کاملVHDL Implementation Of Reconfigurable Crossbar Switch For Binoc Router
Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router crossbar switch. This paper presents implementation of 10x10...
متن کاملOn reconfigurable tiled multi-core programming Processing cores evaluation
For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modelling and programming such systems remains an issue. A semantic model has been presented to allow the development of the model for the specification, design and implementa...
متن کامل